Programmable Digital Signal Processors: Architecture, Programming, and Applications

VLIW Processor Architectures and Algorithm Mappings for DSP Applications
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More and more, these processors are being seen as the dinosaurs of the industry, too encumbered with PC compatibility and desktop features to adapt to the changing real time market place. As the world embraces tiny hand-held wireless-enabled products that require power dissipation measured in milliwatts -not the watts that these processors consume - DSPs are the programmable technology of choice.

That trend is bound to continue as digital Internet appliances get smaller, faster and more portable. The right DSP processor for a job depends heavily on the application. One processor may perform well for some applications, but be a poor choice for others. With this in mind, one can consider a number of features that vary from one DSP to another in selecting a processor.

These features are discussed below. One of the most fundamental characteristics of a programmable digital signal processor is the type of native arithmetic used in the processor. Most DSPs use fixed point arithmetic, while other processors using floating-point arithmetic. Floating-point arithmetic is a more flexible and general mechanism than fixed-point. With floating-point, system designers have access to wider dynamic range the ratio between the largest and smallest numbers that can be represented.

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As a result, floating-point DSP processors are generally easier to program than their fixed point cousins, but usually are also more expensive and have higher power consumption. The increased cost and power consumption result from the more complex circuitry required within the floating-point processor, which implies a larger silicon die. In contrast, on a fixed-point processor, programmers often must carefully scale signals at various stages of their programs to ensure adequate numeric precision with the limited dynamic range of the fixed-point processor.

Most high-volume, embedded applications use fixed point processors because the priority is on low cost and, often, low power. Programmers and algorithm designers determine the dynamic range and precision needs of their application, either analytically or through simulation, and then add scaling operations into the code if necessary.

For applications that have extremely demanding dynamic range and precision requirements, or where ease of development is more important than unit cost, floating-point processors have the advantage. However, such software routines are usually very expensive in terms of processor cycles. Consequently, general-purpose floating-point emulation is seldom used.

A more efficient technique to boost the numeric range of fixed-point processors is block floating point , wherein a group of numbers with different mantissas but a single, common exponent are processed as a block of data. Block floating-point is usually handled in software, although some processors have hardware features to assist in its implementation.

All common floating-point DSPs use a bit data word. For fixed-point DSPs , the most common data word size is 16 bits. The size of the data word has a major impact on cost, because it strongly influences the size of the chip and the number of package pins required, as well as the size of external memory devices connected to the DSP. Therefore, designers try to use the chip with the smallest word size that their application can tolerate. As with the choice between fixed and floating point chips, there is often a trade-off between word size and development complexity.

For example, with a bit fixed-point processor, a programmer can perform double-precision bit arithmetic operations by stringing together an appropriate combination of instructions.

Adaptation of DSP Processors for 3G and 4G Wireless Communication

Of course, double-precision arithmetic is much slower than single-precision arithmetic. If the bulk of an application can be handled with single-precision arithmetic, but the application needs more precision for a small section of the code, the selective use of double-precision arithmetic may make sense. If most of the application requires more precision, a processor with a larger data word size is likely to be a better choice. Note that while most DSP processors use an instruction word size equal to their data word size, not all does.

A key measure of the suitability of a processor for a particular application is its execution speed. A problem with comparing instruction execution times is that the amount of work accomplished by a single instruction varies widely from one processor to another.

Architecture: Programming, and Applications, 1st Edition

Some of the newest DSP processors use VLIW very long instruction word architectures, in which multiple instructions are issued and executed per cycle. These processors typically use very simple instructions that perform much less work than the instructions typical of conventional DSP processors. Although the differences in instruction sets are less dramatic than those seen between conventional DSP processors and VLIW processors, they are still sufficient to make MIPS comparisons inaccurate measures of processor performance.

For example, some DSPs feature barrel shifters that allow multi-bit data shifting used to scale data in just one instruction, while other DSPs require the data to be shifted with repeated one-bit shift instructions. Similarly, some DSPs allow parallel data moves the simultaneous loading of operands while executing an instruction that are unrelated to the ALU instruction being executed, but other DSPs only support parallel moves that are related to the operands of an ALU instruction.

One solution to these problems is to decide on a basic operation instead of an instruction and use it as a yardstick when comparing processors. A common operation is the MAC operation. A more general approach is to define a set of standard benchmarks and compare their execution speeds on different DSPs.

Implementing these benchmarks in a consistent fashion across various DSPs and analyzing the results can be difficult. Second, use caution when comparing processor clock rates. Additionally, many DSP chips now feature clock doublers or phase-locked loops PLLs that allow the use of a lower-frequency external clock to generate the needed high-frequency clock onchip.

Fast MAC execution requires fetching an instruction word and two data words from memory at an effective rate of once every instruction cycle. Another concern is the size of the supported memory, both on- and off-chip. Most fixed-point DSPs are aimed at the embedded systems market, where memory needs tend to be small.

VLIW Processor Architectures

Programmable Digital Signal Processors: Architecture: Programming, and Applications - CRC Press Book. Digital signal processing (DSP) applications on computers have typically used that have been added to current microprocessor instruction set architectures.

As a result, these processors typically have small-to-medium on-chip memories between 4K and 64K words , and small external data buses. In addition, most fixed-point DSPs feature address buses of 16 bits or less, limiting the amount of easily-accessible external memory. Some floating-point chips provide relatively little or no on-chip memory, but feature large external data buses. For example, the Texas Instruments TMSC30 provides 6K words of on-chip memory, one bit external address bus, and one bit external address bus. In contrast, the Analog Devices ADSP provides 4 Mbits of memory on-chip that can be divided between program and data memory in a variety of ways.

As with most DSP features, the best combination of memory organization, size, and number of external buses is heavily application-dependent. The degree to which ease of system development is a concern depends on the application. Engineers performing research or prototyping will probably require tools that make system development as simple as possible.

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That said, items to consider when choosing a DSP are software tools assemblers, linkers, simulators, debuggers, compilers, code libraries, and real-time operating systems , hardware tools development boards and emulators , and higher-level tools such as block-diagram based code-generation environments.

A fundamental question to ask when choosing a DSP is how the chip will be programmed. Typically, developers choose either assembly language, a high-level language—such as C or Ada —or a combination of both. Surprisingly, a large portion of DSP programming is still done in assembly language. Because DSP applications have voracious number-crunching requirements, programmers are often unable to use compilers, which often generate assembly code that executes slowly. Rather, programmers can be forced to hand-optimize assembly code to lower execution time and code size to acceptable levels.

Users of high-level language compilers often find that the compilers work better for floating-point DSPs than for fixed-point DSPs , for several reasons. First, most high-level languages do not have native support for fractional arithmetic. Second, floating-point processors tend to feature more regular, less restrictive instruction sets than smaller, fixed-point processors, and are thus better compiler targets. Third, as mentioned, floating point processors typically support larger memory spaces than fixed-point processors, and are thus better able to accommodate compiler-generated code, which tends to be larger than hand crafted assembly code.

However, even compilers for VLIW processors tend to generate code that is inefficient in comparison to hand-optimized assembly code. Hence, these processors, too, are often programmed in assembly language—at least to some degree. Whether the processor is programmed in a high-level language or in assembly language, debugging and hardware emulation tools deserve close attention since, sadly, a great deal of time may be spent with them. Almost all manufacturers provide instruction set simulators, which can be a tremendous help in debugging programs before hardware is ready.

Is it a separate program from the assembly-level debugger that requires the user to learn another user interface? Most DSP vendors provide hardware emulation tools for use with their processors. Scan-based emulation is especially useful because debugging may be accomplished without removing the processor from the target system.

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The symbol c i represents the corresponding subword in the target register. Please enter your name. The Super Harvard architecture takes advantage of this situation by including an instruction cache in the CPU. Other detailed information about the compression algorithm can be found in the MPEG standard [1]. Sony Semiconductor Company of America. The only difference between these two instructions is in the order of the operands. Bit masks are generated as a result of the comparisons made.

Other debugging methods, such as pod-based emulation, require replacing the processor with a special processor emulator pod. Off-the-shelf DSP system development boards are available from a variety of manufacturers, and can be an important resource. Development boards can allow software to run in real-time before the final hardware is ready, and can thus provide an important productivity boost. Additionally, some low-production-volume systems may use development boards in the final product. Certain computationally intensive applications with high data rates e. In such cases, ease of processor interconnection in terms of time to design interprocessor communications circuitry and the cost of linking processors and interconnection performance in terms of communications throughput, overhead, and latency may be important factors.

ADSPx processors feature bidirectional data and address buses coupled with six bidirectional bus request lines. These allow up to six processors to be connected together via a common external bus with elegant bus arbitration.

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Moreover, a unique feature of the ADSPx processor connected in this way is that each processor can access the internal memory of any other ADSPx on the shared bus. DSPs are increasingly being used in portable applications such as cellular phones and portable audio players where power consumption is a major concern. As a result, many processor vendors are reducing processor supply voltages and adding power management features to give programmers greater influence over processor power consumption.

Power management features available on some DSPs include:. Reduced voltage operation: Many vendors offer low-voltage 3. These processors consume far less power than five-volt equivalents at the same clock rate. In some cases, any unmasked interrupt will bring the processor back from sleep mode, while in other cases, only a few designated external interrupt lines will wake the processor. Then set up a personal list of libraries from your profile page by clicking on your user name at the top right of any screen.

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Please enable cookies in your browser to get the full Trove experience. Skip to content Skip to search. Published New York : Marcel Dekker, c Language English View all editions Prev Next edition 2 of 2. Other Authors Hu, Yu Hen. Physical Description x, p. Series Signal processing and communications ; Subjects Electronic digital computers -- Design and construction.

Signal processing. Contents 1. Managuli and Yongmin Kim 3. Lee and A. Murat Fiskiran 4. Yu and Yu Hen Hu 7. Bhattacharyya 9.